From EP 0 422 776 is known a communication system for serial data exchange which comprises a microprocessor, a memory, a DMA unit (Direct Memory Access Control unit DMAC) and a serial interface (Serial Communication Control SCC). These function blocks are interconnected as shown in FIG. 3 by data bus (column 4, lines 6-26). In FIG. 3 with associated description (column 8, line 41 to column 9, line 12) is described how the data (Communication Line 318) are received from the interface (SCC). Subsequently, under the control of the DMAC, the address information and the message contents of the data packets are written at a fixed memory location in a memory via the data bus (310). In this phase, the interface (SCC) does not supply control signals to the microprocessor via the DMA unit (DMAC). The DMA unit (DMAC) controls the transmission of the data packets from the interface (SCC) to the memory, without a check of the operation and thus a possibility of reacting to deviations from normal operation (column 8, lines 41-47). The DMAC supplies a HOLD signal to the microprocessor only at the end of a data packet to request for a check via the data bus once the SCC signals a request (column 8, lines 51-57) via a line (Request Line 33).
Since the described communication system has no control line from the interface to the microprocessor, this serial interface cannot be operated in the conventional interrupt mode. As a result, the data exchange is always to take place in the DMA mode, in which the DMA unit controls transmission to the memory. Furthermore, without control signals, the interface cannot carry out an accurate check of the data exchange (reception/transmission and storage), so that particularly when there is a deviation from the error-free operation, considerable software expenditure is necessary for correcting measures. In an interrupt mode, the interface directly informs the microprocessor of a data exchange by sending an interrupt signal. This conventional way of controlling the data exchange, however, implies a considerable load of the microprocessor and on the data bus which, as a result, can then render considerably less capacity available for other tasks (for example, the control of further interfaces). For certain data (for example, with the exchange of small data sequences such as control data), this mode, however, is more efficient than the DMA mode in which the direct check is lacking during storage.